The present invention relates to a scan circuit for testing a semiconductor integrated circuit (hereinafter referred to as an “IC”), such as a microcontroller unit (hereinafter referred to as a “MCU”). More particularly, the present invention relates to a scan flip-flop circuit having reduced power consumption during a normal operating mode.
A claim of priority is made under 35 U.S.C. § 119 to Korean Patent Application 2004-45607 filed on Jun. 18, 2004, the entire contents of which are hereby incorporated by reference.
In a semiconductor IC such as a MCU, a competent scan test function is essential to a determination of whether respective logic gates within the MCU operate properly. As the number of logic gates used in contemporary MCU designs has increased, the relative importance of the scan test function has also increased.
A particular type of test circuit is routinely used to implement the scan test function. Generally speaking, this test circuit includes hardware capable of storing test data adapted to establish a defined internal state for the logic gates being tested. Output data is collected in response to the test data. The output data indicates whether the logic gates are operating normally or in error. This generic type of test circuit is termed a “scan flip-flop circuit”.
FIG. 1 is a circuit diagram showing a conventional scan flip-flop circuit 100. Referring to FIG. 1, the conventional scan flip-flop circuit 100 includes an input stage 116, a D flip-flop 110, and an output stage 118. The scan flip-flop circuit 100 has four input terminals D, TI, TE, and CK, and two output terminals Q and QN. The input terminal includes a mode input terminal TE, a normal input terminal D, a scan input terminal TI, and a clock input terminal CK. An operating mode signal is applied to mode input terminal TE, a normal logic signal is applied to normal input terminal D, a scan logic signal is applied to scan input terminal TI, and a clock signal is applied to clock input terminal CK. The first output terminal Q receives one of the normal logic signal or the scan logic signal which are applied to the normal input terminal D and the scan input terminal TI, respectively. The first output terminal Q produces an output in accordance with the clock signal. The second output terminal QN similarly receives either the normal logic signal or the scan logic signal, inverts the received signal, and outputs the result in accordance with the clock signal.
Input stage 116 of scan flip-flop circuit 100 selects between the normal logic signal and the scan logic signal in accordance with a defined operating mode for the scan flip-flop circuit 100, and outputs the selected logic signal to the D flip-flop 110. Input stage 116 includes a first AND gate 104, a second AND gate 106, and a NOR gate 108. First AND gate 104 ANDs the normal logic signal and an inverted operating mode signal. Second AND gate 106 ANDs the scan logic signal and an operating mode signal. NOR gate 108 NORs an output of first AND gate 104 and an output of second AND gate 106. Accordingly, input stage 116 selects and outputs the normal logic signal when scan flip-flop circuit 100 operates in a normal mode (TE=‘0’), and selects and outputs the scan logic signal when scan flip-flop circuit 100 operates in a scan mode (TE=‘1’).
Unfortunately, the input stage of the conventional scan flip-flop circuit is characterized by a large number of transistors which are necessary to implement the plurality of logic gates. Because of this large number of transistors, the conventional scan flip-flop circuit occupies a considerable space within the semiconductor IC and generally reduces the overall degree of device integration.
Returning to FIG. 1, D flip-flop 110 includes one input terminal which receives either the normal logic signal or the scan logic signal from input stage 116 and outputs the received logic signal in synchronism with the clock signal. Typically, D flip-flop 110 of scan flip-flop circuit 100 is triggered on a rising edge of the clock signal. Operation and construction of the D flip-flop is conventional. In a case where a rising clock edge is applied to a clock (or gating) terminal of D flip-flop 110, the D flip-flop will output a signal having a logic value of ‘1’ when the received input signal has a logic value of ‘1’, and will output a signal having a logic value of ‘0’ when the received input signal has a logic value ‘0’. D flip-flip 110 also delays its output relative to the received input signal by a time interval up to the period of the clock signal.
Output stage 118 includes first and second inverters 112 and 114, which are respectively connected to output terminals Q and QN of D flip-flop 110. First and second inverters, 112 and 114, respectively invert signals to be output from first and second output terminals Q and QN of D flip-flop 110.
Table 1 is a truth table showing values output from output terminals Q and QN and corresponding values applied to the respective input terminals D, TI, TE, and CK in the conventional scan flip-flop circuit shown in FIG. 1. Here, Q(n+1) indicates an output corresponding to an (n+1)th clock signal.
TABLE 1DT1TECKQ(n + 1)QN(n + 1)0x0Rising011x0Rising10x01Rising01x11Rising10xxxFallingQ(n)QN(n)
FIG. 2 is a circuit diagram illustrating an example of a scan chain circuit and its operation using a plurality of scan flip-flop circuits like the one shown in FIG. 1. As shown in FIG. 2, the scan chain is composed of five scan flip-flip circuits 202, 204, 206, 208, and 210, and two combinational logic circuits 212 and 214. It is assumed that three scan flip-flip circuits 202, 204, and 206 each respectively receive externally applied normal logic signals when a scan chain operates at a normal mode. It is further assumed that each of the combinational logic circuits 212 and 214 includes at least one output terminal and at least two input terminals. Logic states for signals apparent at the respective output terminals of the combinational logic circuits 212 and 214 are determined by the respective states of signals simultaneously applied to the corresponding input terminals.
The scan chain includes three normal input terminals IN1, IN2, and IN3, one scan input terminal SCAN_IN, a mode input terminal TEST, a clock input terminal CLK, and one output terminal OUT or SCAN_OUT. An externally derived normal logic signal is applied to the three normal input terminals IN1, IN2, and IN3, a scan logic signal is applied to the scan input terminal SCAN_IN, an operating mode signal is applied to the mode input terminal TEST, and a clock signal is applied to the clock input terminal CLK. As shown in FIG. 2, a scan input terminal SCN_IN to which an externally derived scan logic signal is applied, is connected to only the scan input terminal TI of a first scan flip-flip circuit 202. The scan input terminals TI for the other scan flip-flop circuits (204, 206, 208, and 210) are connected in a cascade fashion from the output terminals Q of a previous scan flip-flip circuit to a following scan input terminal of a next scan flip-flop circuit, thereby forming a chain configuration or arrangement. In such a scan chain, signal racing due to clock skew is prevented by inserting nil cells (nil1, nil2, nil3, and nil4 ) are respectively inserted between an output terminal Q and a corresponding scan input terminal T1 in the cascade.
On the other hand, when the scan chain circuit of FIG. 2 operates in scan mode (TE=1), each of the scan flip-flip circuits performs a scan operation in response to a signal applied through its scan input terminal TI, and outputs a scan test result through scan flip-flop circuit 210 which forms a final stage for the scan chain. In contrast to this operation, when the circuit of FIG. 2 operates in a normal mode (TE=0), each scan flip-flop circuit operates in response to a signal applied through a normal input terminal D, regardless of the signal applied through scan input terminal TI. That is, when the circuit of FIG. 2 operates in normal mode (TE=0), the signal applied through a scan input terminal TI for each scan flip-flop circuit is not used during normal operation of the circuit. However, as indicated at Table 1, when the circuit of FIG. 2 operates in normal mode (TE=0), each scan flip-flop circuit will nonetheless continuously toggle in its state in response to the signal applied to its scan input terminal TI in from the preceding output terminal Q. This useless signal level switching consumes considerable power.